FIG. 15 shows a stacked capacitor DRAM manufactured by a first conventional method. As shown in FIG. 15, with increasing an integration level in a stacked capacitor DRAM, there is a trend that a storage node electrode 12 and a plate electrode 13 of a capacitor 11 are increasingly three-dimensionalized such as to secure a required memory cell capacitance in spite of a small plane surface area of the memory cell.
In the first conventional method as shown in FIG. 15, however, the height of the memory cell is increased by the three-dimensionalized storage node electrode 12, which result in an increase in the step 23 between the memory cell array portion 15 and the peripheral circuit portion 16. For this reason, a focus margin is small during a light exposure in a lithography process after the capacitor 11 has been formed. It causes the difficulty of patterning of a fine bit line 24, and an Aluminum wiring 25, or manufacturing of a DRAM with high yield was not feasible hitherto.
FIG. 16 shows a stacked capacitor DRAM manufactured by a second conventional method. In this second method, the surface of an silicon substrate 14 in the memory cell array portion 15 is lowered relative to that in the peripheral circuit portion 16. In order to achieve this structure, first, an oxidation is carried out under a condition that the peripheral circuit portion 16 is covered with an oxidation-resistant SiN (Silicon nitride) film 17. Thus, as shown FIG. 17, a thick SiO.sub.2 (Silicon dioxide) film 18 is formed on the surface of the memory cell array portion 15.
Next, as shown in FIG. 18, both the SiN film 17 and the SiO.sub.2 film 18 are removed so that the surface of the memory cell array portion 15 is lowered relative to that of the peripheral circuit portion 16. Thereafter, another oxidation is carried out under a condition that an active region of the memory cell array portion 15 and the peripheral circuit portion 16, respectively, is covered with an SiN film 21 so that an SiO.sub.2 film 22 for an isolation is formed.
In the second conventional method, the step between the memory cell array portion 15 and the peripheral circuit portion 16 after the formation of the capacitor 11 can be moderated, compared to the first conventional method. However, as shown in FIG. 16, an excessive film thickness of the SiO.sub.2 film 18 to sufficiently moderate the step will increase a step 26 between the memory cell array portion 15 and the peripheral circuit portion 16 before the formation of the capacitor 11.
For this reason, a focus margin is too small during light exposure in a lithography process on patterning of the SiO.sub.2 film 22, a gate electrode 27 and the like. Therefore, manufacturing of a DRAM with high yield was not feasible according to the second conventional method, too. On the other hand, since the storage node electrode 12 and the plate electrode 13, both constituting the capacitor 11, are formed only in the memory cell array portion 15, patterning of these is uninfluenced by the steps 23 and 26 and hence relatively easy by nature.